Types of Synthesis

Types of Synthesis #

Logical Synthesis #

Logical synthesis processes the HDL (Verilog or VHDL) design and generates gate level netlist. During this process, the compiler optimizes the design based on predefined constraints.

Physical Aware Synthesis

Physical Aware synthesis requires additional floorplan DEF as an input. Floorplan DEF contains physical information like IO ports placements, macro placement information, blockages information and die area information. Additionally, we use RC co-efficient file as one of the inputs to compute a more accurate wire delay values compared to the WLM (Wire Load Model) method.

Advantages of Physical Aware synthesis:

1. Better PPA (Power, Performance, Area).
2. Better timing correlation with PNR.
3. Better turnaround time (reduces the number of iterations).

Logic Aware Synthesis

Physical Aware Synthesis

Inputs :

RTL , UPF , Libraires ,Constriants

To calculate the Net delays Wire Load Models are used .
Uncertainity is More
PPA is not accurate compare to Physical aware synthesis
Runtime is Less compare to Physical aware Synthesis
It is called as One pass Synthesis

Inputs :

RTL , UPF ,Libraries , Constriants
.tf (Technology Files)
TLU +files for RC Extraction
Floor Plan DEF

TLU +files are used to calculate the Net delays .
Uncertainity is Less
We use Floor Plan DEF as a input to get Better PPA
Runtime is More compared to Logic Aware Synthesis
It is called as two pass Synthesis

VLSI

Linux Commands

Electronics Revision

Introduction To VLSI

CAD for VLSI

Synthesis

Physcial Design Inputs

Floorplan

Placement

Types of Synthesis