Inputs and Outputs Files in Synthesis #
- Input Files:
Fig 1. Inputs and outputs in Synthesis Flow
- Technology related:
- Target Library
- The target library is the technology library you want to map to during synthesis. It is also known as the destination library.
- Specify the target library with the pointer variable target_library.
- Link Library
- The link library is a technology library that is used to describe the function of mapped cells prior to optimization.
- Specify the link library with the variable pointer link_library.
- Typically, the link and target library are set to the same technology library.
- .lib-timing info of standard cell & macros
- Design related:
- .v- RTL code. : It’s a descriptive code written in HDL format.
- SDC- It represents the design constraint.
- UPF- UPF file is required to describe the power intent of the design including the power domain, level shifter, isolation cell, and retention registers.
- Scan config- Scan related info like scan chain length, scan IO, which flops are to be considered in the scan chains.
- Physical aware related:
- RC co-efficient file (tluplus).
- LEF/FRAM- LEF represents the physical information of metal and via, standard cell, and macro.
- Floorplan DEF- DEF file contains the placement information of macro, pre-placed cells, IO ports, block size, and blockages. Mainly used for the Physical Aware synthesis.
- Output Files:
A qualified netlist with scan insertion and good QoR in terms of timing, power, and area. Other outputs are updated DEF, UPF, SDC, and ScanDEF.
- UPF: The output UPF is the updated version of the input UPF. At the synthesis stage, it performs logic optimization that introduces new power intents. So, we are generating UPF with this update after synthesis.
- DEF: While performing Physical Aware synthesis, we also generate the DEF file, which contains macro and standard cell placement information. This DEF is directly used in physical implementation that, avoids placement of the cell from scratch, hence, we can save run time.
- SDC: The output SDC is the updated version of the input SDC. At the synthesis stage, we use constraints provided by the designer. Additionally, we use certain local constraints to improve the overall QoR of design. Thus, the SDC with this update is generated after synthesis.
- ScanDEF– information of scan flops and their connectivity in a scan chain