SYNTHESIS FLOW IN VARIOUS TOOLS #
Cadence – Genus Flow : #
Synthesis Flow
We had Followed guidelines of the Genus Flow
- Syn_generic
- Syn_map
- Scan insertion/Scan chain
- Syn_opt
Takes an elaborated and fully constrained design as input and synthesizes it into a netlist of generic gates by doing high-level RTL and datapath optimizations.
- Using enable conditions in the fanin of registers to implement clock-gating logic and thus reducing power. The main attribute to enable this feature is lp_insert_clock_gating (default is off). For details refer to the other related attributes in the lp_cg category.
- Apply retiming to improve overall maximum performance of the design. This technique is applied to all modules tagged with the retime attribute. Further control is possible via attributes of the retime category.
It is recommended to use the check_design command in advance to find major design problems like unresolved modules and multi-driven or undriven nets or pins. Also, the command check_timing_intent helps to identify issues related to the timing constraints read into the tool.
If the -physical option is specified, Genus will also place the generic netlist and compute an initial congestion map based on actual global routing that enables the user to rate the quality of the given floorplan. Top paths are physically optimized, so timing bottlenecks of the design can be identified quickly. The resulting database can be used to analyze congestion and critical path placement even before mapping to the technology library. Use the check_floorplan command in advance to ensure the given floorplan data is of high quality.
syn_generic_effort medium
Maps a design from generic gates to a technology library while optimizing for best performance, power and area. Genus evaluates multiple implementations for a given logic cone and chooses the one that meets timing constraints while minimizing area and power. After an initial mapping phase, further refinement is done by incrementally optimizing the netlist to recover area and power while maintaining timing.
- Structuring and mapping of generic logic to meet specified goals. Certain features of optimization can be controlled via attributes. For a full list of these attributes, refer to the opt category using get_db * -category opt.
- Selective ungrouping of modules to improve optimization for best timing or area. This can be controlled via the auto_ungroup attribute.
- Optimizing for leakage and dynamic power. The effort spent on reducing leakage power is specified via the leakage_power_effort attribute. By default, Genus does not optimize for power.
- Mapping of single-bit to multi-bit library cells. By default this feature is turned off, but it can be enabled via the use_multibit_cells attribute.
The library cell set available to the mapper can be restricted by applying the dont_use attribute to library cell objects. It is recommended to only apply this attribute in case certain library elements are not allowed to be used under any circumstances and not as an overall guidance to the mapping engine.
If the -physical option is specified, Genus will perform physical-aware mapping and restructuring of logic to account for physical effects like long wires in the design. Placement locations of registers are maintained throughout mapping to allow for physical-aware multi-bit merging of flip flops and physical-aware scan insertion post syn_map. It is a prerequisite to run physical-aware mapping if syn_generic was run in physical mode too.
set_db OPT_EFF medium
Takes a mapped design as input and incrementally optimizes timing, area and power. Without specifying the spatial or physical flow options, syn_opt will do pure logical optimization, even if called on a design database that was generated by physical-aware mapping. Depending on the effort level specified by the syn_opt_effort attribute, it first optimizes worst and total negative slack, then applies certain transforms to recover area and power. The higher the effort, the more iterations of optimization steps are done.
Multiple features of incremental optimization (for example, timing-driven duplication of registers) can be controlled via attributes, for a full list of these check the iopt category (get_db * -category iopt).
Synopsis – DC Flow #
Synthesis Flow in DC
Synthesis input #
- LIB: The timing library (.lib) contains information related to the timing, power, and area of standard cells. It also contains different PVT characterizations of cells.
- LEF: LEF represents the physical information of metal and via, standard cell, and macro.
- RTL: It’s a descriptive code written in HDL format.
- SDC: It represents the design constraint.
- DEF: DEF file contains the placement information of macro, pre-placed cells, IO ports, block size, and blockages. Mainly used for the Physical Aware synthesis.
- UPF: UPF file is required to describe the power intent of the design including the power domain, level shifter, isolation cell, and retention registers.
Elaboration #
At this stage, it reads the RTL code, and this RTL code is converted into modules as per its logical hierarchy. Once it has all logical Boolean representation loaded, the tool maps logic with a technology-independent cell called the Gtech cell.
During elaboration, the tool checks whether the design is unique, if not, it stops the tool. Once the design becomes unique, the tool checks for unresolved references in the design. If it has linking issues, then an RTL correction is required, or you need to check if it is due to any missing libraries. After elaboration, it checks for timing loops in design. If you find any timing loop, you need to get RTL correction done by the designer.
Compile and optimization #
After elaboration, in the compilation stage, the tool maps the Gtech cell with the actual cell (specific technology dependent) from the library. Actual cell mapping is dependent on the design constraints or user-specific constraints. Apart from this, the tool removes the registers with constant propagation/unloaded which are not required in the design. If these removed cells are required, then you need to provide feedback to the designer to get the correct RTL.
After elaboration and compilation, the tool performs optimizations based on user constraints to meet timing, area, and power requirements.
DFT #
The Design for Testability (DFT) stage performs the scan insertion in the optimized design. After this stage, the design should fulfill the scan criteria and achieve the desired scan coverage.
Outputs #
A qualified netlist with scan insertion and good QoR in terms of timing, power, and area. Other outputs are updated DEF, UPF, and SDC.
- UPF: The output UPF is the updated version of the input UPF. At the synthesis stage, it performs logic optimization that introduces new power intents. So, we are generating UPF with this update after synthesis.
- DEF: While performing Physical Aware synthesis, we also generate the DEF file, which contains macro and standard cell placement information. This DEF is directly used in physical implementation that, avoids placement of the cell from scratch, hence, we can save run time.
- SDC: The output SDC is the updated version of the input SDC. At the synthesis stage, we use constraints provided by the designer. Additionally, we use certain local constraints to improve the overall QoR of design. Thus, the SDC with this update is generated after synthesis.