Practical Exposure at Synthesis and Real Time Debug #
RTL issues:
If we are experiencing any RTL issues (issues means Syntax Errors , ..) in synthesis – we should discuss with the Design Team .
Error : Parsing Error [VLOGPT-1] [read_hdl]
: in file ‘path of Verilog file – .v‘ , line number 10 ,column number :100
Invalid Verilog syntax is parsed, or unsupported Verilog syntax is encountered.
Unresolved References :
- Error : Could not resolve reference. [CDFG-431] [elaborate]
Solution : Adding the Missing Libraries and LEF’s in the Design.
Blackbox :
- If any we did not had Lib’s or LEF ‘s of single block – for the time being we should black box it . Command for Setting the Black Box for single Block .
set_db [get_db hdl_architectures Blockname ] .blackbox true
Resolving Mapping Issue :
Error : Unable to map design without a suitable flip-flop. [MAP-2]
- set_db / .treat_non_seq_arc_cell_as_unusable false
- If attribute ‘timing_disable_non_sequential_checks’ is set to false, cells having non sequential setup arcs are marked as unusable.There is a change in the behaviour .This behaviour is default ON from 19.10 onwards.
- If you do not want such cells to be marked as unusable, attribute ‘treat_non_seq_arc_cell_as_unusable’ needs to be set to false.
- Cells having non-seq arcs will be timed if attribute ‘timing_disable_non_sequential_checks’ is set to false.
- As it is wrong to map generic flops to libcell having non-seq arcs due to different timing caused by non-seq arcs such as no min_delay, combo loops, etc.., such cells are marked as unusable when above attribute is set to false.
Scan chain issue :
- Previously we used old flow for synthesis , The scan chains are built by the tool after the optimization . But in the newer versions we are experiencing the
“Error: Failed to connect scan chains “
- But as per the Genus ispatial Flow guidelines prior to optimization we should perform the Scan chain/scan Insertion. Then connect the scan chain is done successfully in our design.
Timing Issue:
- In the design the path related to TI pin is violating in Functional Mode . And the Violation is nearly -60 ns. This timing is traced and found that the path is unexpected then we set it in to False path in the interactive constraint mode.
foreach av [get_db designname .setup_views] {
set view [basename $av]
set cm [basename [get_db $av .constraint_mode]]
if {[regexp “func” $cm match]} {
set_interactive_constraint_modes $cm
set_false_path -through [get_pins -hier instancename]
set_interactive_constraint_modes {}
}
}
Check_Design :
LINT-1
LINT-1 (warning) In design ‘%s’, cell ‘%s’ does not drive any nets.
DESCRIPTION : This warning alerts you that the output(s) of a component is not connected to any load nets. This usually indicates that a design has not been correctly specified. The Design Compiler may remove such components from your design unless they are protected by a dont_touch attribute.
WHAT NEXT: Make sure that you really want the named component to exist in the given design, even though it has no output pins connected. If so, add a dont_touch attribute with the dont_touch command to keep the component from being removed
LINT-2
LINT-2 (warning) In design ‘%s’, net ‘%s’ driven by pin ‘%s’ has no loads.
DESCRIPTION : This warning message occurs when a net is driven by an output pin (or pins) but has no load pins connected to it. This usually indicates that a design is not correctly specified. The Design Compiler may remove such nets and their driving components from your design unless they are protected by a don’t touch attribute.
WHAT NEXT: This is only a warning message. You can eliminate this warning message by following the instructions below. Make sure that you want the named net to exist in the given design, even though it has no load pins connected. If so, add a don’t touch attribute with the dont_touch command to keep the net from being removed. Check the value of the hdlin_keep_signal_name variable. For some settings, signals without drivers or loads are preserved in the elaborated design. Check the hdlin_keep_signal_name man page for more information
LINT-28
LINT-28: (warning) In design ‘%s’, port ‘%s’ is not connected to any nets.
DESCRIPTION: This warning alerts you that a port in a design is not connected to any nets. This usually indicates that a design has not been correctly specified. However, there are some situations where, as a designer, you choose to specify a port on a design for compatibility reasons, even though the port is not internal to design use. The Synopsys tools leave unconnected ports alone, with one exception; that is, you specified that a given input port is opposite or equal to another input port in a design.
WHAT NEXT Make sure that you want the named port to exist in the given design, even though it has no nets connected. Remove the port from your design if you choose.
LINT-29
LINT-29: (warning) In design ‘%s’, input port ‘%s’ is connected directly to output port ‘%s’.
DESCRIPTION: This warning alerts you to a situation where an input port in a design is directly connected to an output port. This warning is issued because some technologies do not allow such a connection. Many ASIC vendors stipulate that a buffer must be used to connect an input to an output. This restriction might or might not apply to your technology.
WHAT NEXT: If directed to do so, compile inserts the necessary buffering to prevent a direct connection of an input port and an output port. To do this, set the boolean variable compile_fix_multiple_port_nets to TRUE, then compile your design. This variable also instructs compile to make sure that multiple output ports are not connected to the same electrical net. See the manual page on compile_variables for more information.
LINT-31
LINT-31: (warning) In design ‘%s’, output port ‘%s’ is connected directly to output port ‘%s’. DESCRIPTION: This warning alerts you to a situation where an output port in a design is connected directly to another output port. This warning is issued because some technologies do not allow such a connection. This restriction might or might not apply to your technology.
WHAT NEXT: If directed to do so, compile inserts the necessary buffering to make sure that multiple output ports are not connected to the same electrical net. To do this, set the boolean variable compile_fix_multiple_port_nets to TRUE, then compile your design. This variable also instructs compile to prevent a direct connection of an input port and an output port. See the manual page on compile_variables for more information.
LINT-32
LINT-32: (warning) In design ‘%s’, a pin on submodule ‘%s’ is connected to logic 1 or logic 0. DESCRIPTION: check_design issues this warning when it finds an instance of a hierarchical design(for example, a sub-module) that has an input connected to a logic constant. This warning is issued to verify that this is a desired connection on the submodule. Be aware that compile can remove logic in a design that is redundant. So, compile can produce designs that display this warning if it has optimized and eliminated the logic driving a submodule.
WHAT NEXT: Verify that you want the given submodule input connected to logic one or zero. If you have run compile, you might want to use verify to verify the optimized design with your original. Or, use the -verify option to compile, whenever feasible.
LINT-33
LINT-33: (warning) In design ‘%s’, the same net is connected to more than one pin on submodule ‘%s’.
DESCRIPTION: check_design issues this warning when it finds an instance of a hierarchical design (for example, a sub-module) that has more than one input connected to the same net. This warning is issued to verify that these are desired connections on the submodule. Be aware that compile can remove logic in a design that is redundant. So, compile can produce designs that display this warning if it determines that multiple inputs on a submodule are driven by the same logical signal.
WHAT NEXT Verify that you want the given submodule inputs connected to the same logical signal. If you have run compile, you might want to use verify to verify the optimized design with your original. Or, use the -verify option to compile whenever feasible.
LINT-52
LINT-52: (warning) In design ‘%s’, output port ‘%s’ is connected directly to ‘%s’.
DESCRIPTION: This warning alerts you to a situation where an output port in a design is connected directly to Logic 1 or Logic 0. This warning is issued because some technologies do not allow such a connection. This restriction might or might not apply to your technology. Most case it is a design error.
WHAT NEXT: Please check the net list carefully to make sure this case is desired, and discuss with your technology team to make sure it is allowed.
LINT-60
LINT-60: (warning) In design ‘%s’, input pin ‘%s’ of hierarchical cell ‘%s’ has no internal loads and is not connected to any nets.
DESCRIPTION: This message appears when hierarchical cell input pin has no internal load and no driver. Synopsys tools assume a logical value (for example, logic zero or logic one) for such unconnected signals, based on the type of technology library you are using. This warning message is a notification of the assumption that is being made for the named input pin in the named design. WHAT NEXT: Verify that the assumption made by Synopsys regarding the logical value for the given signal is correct. If the assumption is not correct, then connect the floating input pin to the correct logical value in your design.
-
-
- Timing related :
-
After report_global_timing we get WNS, TNS and NVPs in in various path groups.
Using this information, we can determine which path group has higher no. of NVPs or (-) WNS so that either we can work on those or we can inform FE/SDC team.
Timing Analysis and Debug at Synthesis Stage
Debugging Timing Issues: Observing Huge Negative Slack in the Timing Path
Note: If the negative timing slack is huge and there are many paths with such slack values, this is probably a setup issue. Check if there are any errors in the log file or any warnings as mentioned in the placement article. Fix those errors and rerun it.
CASE 1: Instance or net is preserved.
- Regarding preserve instances
An example timing path is shown below.
Path 1: VIOLATED (-351 ps) Setup Check with Pin RAM_256x16_TEST_INST_RAM_256x16_INST/CLOCK->ADDRESS[2]
View: view_wcl_fast
Group: m_dsram_clk
Startpoint: (R) TDSP_CORE_INST/EXECUTE_INST/arp_reg/CK
Clock: (R) clk2x
Endpoint: (F) RAM_256x16_TEST_INST_RAM_256x16_INST/ADDRESS[2]
Clock: (R) m_dsram_clk
Capture Launch
Clock Edge:+ 16000 15000
Src Latency:+ 0 0
Net Latency:+ 0 (I) 0 (I)
Arrival:= 16000 15000
Setup:- 985
Required Time:= 15015
Launch Clock:- 15000
Data Path:- 366
Slack:= -351
#————————————————————————————————————————————–
# Timing Point Flags Arc Edge Cell Fanout Load Trans Delay Arrival Instance
# (fF) (ps) (ps) (ps) Location
#————————————————————————————————————————————–
TDSP_CORE_INST/EXECUTE_INST/arp_reg/CK <<< – R (arrival) 35 – 0 – 15000 (-,-)
TDSP_CORE_INST/EXECUTE_INST/arp_reg/Q (#,P) CK->Q R SDFFRHQX4 15 22.2 34 90 15090 (440.0000,184.3000)
TDSP_CORE_INST/g20547/Y (#,P) B->Y F NAND2XL 1 1.3 31 24 15114 (431.4000,155.2300)
TDSP_CORE_INST/g17368/Y (#) B0->Y R OAI21X1 2 5.6 47 20 15134 (433.0000,155.2300)
TDSP_CORE_INST/g19948/Y (#) A1->Y F AOI21X2 2 7.2 32 29 15163 (442.1210,164.2975)
TDSP_CORE_INST/g20606/Y – A->Y R NOR2X2 2 6.3 26 21 15184 (429.7015,178.4385)
TDSP_CORE_INST/g197/Y (#) B->Y F NAND2X2 3 4.0 25 19 15204 (424.5680,182.2975)
TDSP_CORE_INST/g182/Y (#) A->Y R INVXL 2 3.5 22 17 15221 (420.1890,188.0760)
TDSP_CORE_INST/g21222/Y – B->Y R AND2X1 3 3.5 25 39 15260 (413.7445,192.4935)
TDSP_CORE_INST/g2/Y (#) B0->Y F AOI2BB1X1 1 3.4 25 19 15279 (413.2000,192.8500)
fplctnsbuf_star6986/Y – A->Y R INVX3 3 11.9 16 14 15292 (408.0600,192.8500)
g22/Y – B1->Y F AOI2BB2X1 1 2.8 45 23 15316 (376.8250,210.3775)
g6881/Y – A->Y R INVX2 1 10.1 39 29 15345 (373.0750,213.5125)
fplctnsbuf_la_st6247/Y (#) A->Y F INVX12 1 65.9 17 14 15359 (371.2000,215.0800)
RAM_256x16_TEST_INST_RAM_256x16_INST/ADDRESS[2] <<< (P) – F CDK_S256x16 1 – – 6 15366 (44.0000,221.1800)
#————————————————————————————————————————————–
(#) : Net either has Non-default Routes or has been promoted to higher metal layers.
(P) : Instance is preserved
In this timing path, the TDSP_CORE_INST/EXECUTE_INST/arp_reg and TDSP_CORE_INST/g20547 instances are preserved, which is indicated by the symbol “P”. In this case, the tool cannot resize them or remap them to a high drive strength cell.
If these instances are preserved by the user, then after mapping, you can set the value of preserve to “size_ok” instead of “true” so that resizing can take place.
One case where Genus inserts and preserves the instances is while removing the assign statements. If you do not want them to be preserved, set the preserve attribute as false on the rm_assign* buffers after insertion of assign buffers.
- Regarding preserved nets
You can report the timing path along with the net information by using the “-nets” option with the report_timing command as shown below.
report_timing -from TDSP_CORE_INST/EXECUTE_INST/arp_reg/CK -to RAM_256x16_TEST_INST_RAM_256x16_INST/ADDRESS\[2\] -nets
From the above report, take the net name and check ‘preserve’ on it. When a net is preserved even though the net length is more, Genus or Innovus cannot buffer these paths resulting in a huge delay.
Another way to find the net name is by using the net attribute for the pin.
Common UI:
@genus:root: > get_db pin:dtmf_recvr_core/TDSP_CORE_INST/EXECUTE_INST/arp_reg/Q .net
net:dtmf_recvr_core/TDSP_CORE_INST/arp
Legacy UI:
legacy_genus:/> get_attribute net dtmf_recvr_core/TDSP_CORE_INST/EXECUTE_INST/arp_reg/Q
/designs/dtmf_recvr_core/instances_hier/TDSP_CORE_INST/instances_hier/EXECUTE_INST/nets/arp
To check the preserve attribute on the nets:
Common UI:
@genus:root: > get_db net:dtmf_recvr_core/TDSP_CORE_INST/arp .preserve
true
If these are set by the user, set the preserve attribute to false so that the tool can buffer these nets.
CASE 2: Observing timing degradation on reset paths.
In Genus, the nets connected to asynchronous pins are considered as ideal. By default, the asynchronous and ideal pins are represented by the symbol “a” and ” i ” respectively, in the timing report.
As the nets are ideal, these cannot be buffered. To avoid this, set the attribute shown below before “syn_gen -physical”.
Common UI:
@genus:root:> set_db design:dtmf_recvr_core .ideal_seq_async_pins false
Setting attribute of design ‘dtmf_recvr_core’: ‘ideal_seq_async_pins’ = false
1 false
Legacy UI:
legacy_genus:/> set_attribute ideal_seq_async_pins false /designs/*
Setting attribute of design ‘dtmf_recvr_core’: ‘ideal_seq_async_pins’ = false
How to analyze or debug congestion in Genus Physical or iSpatial synthesis # |
- How to report congestion in Genus.
- How to analyze congestion in GUI and save a snapshot.
- How to store the congestion information and load it in another session.
- How to decrease congestion in the Genus Physical or iSpatial synthesis.
Answer:
Reporting congestion in Genus
The command to report congestion in Genus is “report_congestion”. You can use the same command in both Legacy UI and Common UI. An example is shown below.
legacy_genus:/> report_congestion
============================================================
Generated by: Genus(TM) Synthesis Solution 19.14-e045_1
Generated on: May 05 2020 12:37:02 am
Module: dtmf_recvr_core
Library domain: timing_cond_wcl_slow
Domain index: 0
Technology libraries: slow
PLL_worst
CDK_S128x16 0.0
CDK_S256x16 0.0
CDK_R512x16 0.0
physical_cells
Operating conditions: slow
Interconnect mode: placement
Area mode: physical library
Routing: spatial
============================================================
H overflow : 0.00%
V overflow : 0.01%
Total number of GCELLS: 66564
How to highlight congestion and save a snapshot in Genus Physical GUI (Layout viewer) #
Before you highlight or save a snapshot, open GUI by using the “gui_show” command. Then select Congestion and Density Map, which are on the right of the Layout viewer as shown below. Make the design fit to the screen.
After the above highlight is done, use the “gui_pv_snapshot“ command on the Genus shell to save this snapshot (for example, “gui_pv_snapshot congestion_density.gif”). By default, the snapshot is saved in a .gif format. To save it in a .png format, use the -png option with the gui_pv_snapshot command.
If you want only congestion to be saved in the snapshot, use the -congestion option with the “gui_pv_snapshot -congestion congestion.gif” command.
Saving and restoring the congestion data #
You can write or save the congestion map information after syn_opt -spatial using the commands given below. You can read or restore the data in a new session after reading the DEF file in a new session.
Make sure there are no major design changes in the two sessions like RTL or DEF.
Commands to write or save the congestion map:
Legacy UI: save_congestion_map <file_name>
Common UI: genus:root:> write_congestion_map congestion_map
Commands to read or restore the congestion map:
Legacy UI: restore_congestion_map <file_name>
Common UI:
genus:root:> read_congestion_map congestion_map
Checking out license: Genus_Physical_Opt
Reading congestion map file ‘congestion_map’…
Tips to reduce congestion in Genus physical or iSpatial synthesis #
a)Avoid the usage of complex cells in the designs.
You can increase the area multiplier of complex cells i.e. libcells that have ‘libpins greater than 4’ before syn_map by using the following command.
Legacy_UI:
legacy_genus:/> foreach libcells_name [find / -libcell * ] { if { [llength [filter pg_type invalid [find $libcells_name -libpin * ]] ] > 4 } { set_attr area_multiplier 2.0 $libcells_name }}
Setting attribute of libcell ‘OA22XL’: ‘area_multiplier’ = 2.0
Setting attribute of libcell ‘OAI222XL’: ‘area_multiplier’ = 2.0
Common_UI:
genus:root > get_db lib_cells -foreach { if { [llength [get_db $object .lib_pins -if { .pg_type == invalid } ]] > 4 } { set_db $object .area_multiplier 2.0 } }
Setting attribute of lib_cell ‘OA22XL’: ‘area_multiplier’ = 2.0
Setting attribute of lib_cell ‘OAI222XL’: ‘area_multiplier’ = 2.0
Note: Reset the area_multiplier attribute to 1.0 (default value) immediately after syn_opt as it might result in false QOR reports in terms of the area as you have changed the default value of area_multiplier.
To reset the area_multiplier to default 1.0 for all libcells, use the following commands:
Legacy_UI:
legacy_genus:/> set_attribute area_multiplier 1.0 [find / -libcell *]
Setting attribute of libcell ‘OA22XL’: ‘area_multiplier’ = 1.0
Setting attribute of libcell ‘OAI222XL’: ‘area_multiplier’ = 1.0
Common_UI:
genus:root > set_db [get_db lib_cells] .area_multiplier 1.0
Setting attribute of lib_cell ‘OA22XL’: ‘area_multiplier’ = 1.0
Setting attribute of lib_cell ‘OAI222XL’: ‘area_multiplier’ = 1.0
Caution: This can increase the area of the design as you are not using many complex libcells.
b) Using the effort levels in Genus and Innovus scripts.
For a high congestion design, you can change the effort levels using the attributes shown below.
In iSpatial, where Innovus palcer is used underhood Genus ispatial flow.
Genus commands
Common UI:
For iSpatial flow, use the following attributes:
set_db congestion_effort high
set_db pqos_placement_effort high
For iSpatial, use the following attribute:
set_db opt_spatial_cong_effort high
For Legacy UI, replace set_db with set_attribute in the above commands.
Innovus commands
These attributes can be placed in a script. This script can be provided with the “invs_postload_script” attribute in Genus.
Common UI:
set_db design_cong_effort high
set_db place_global_cong_effort high
set_db plan_design_cong_aware true
Legacy UI:
setDesignMode -congEffort high
setPlaceMode -place_global_cong_effort high
setPlanDesignMode -congAware true
If Genus Common UI is used, use Innovus Common UI commands in the script.
Caution: Using these attributes will increase both Genus and Innovus runtime, use it only if needed.
Note: Starting with the Genus 21.X version, support for the Innovus postload script has been discontinued, and a majority of Innovus commands used in the postload script are now supported within Genus.
c) Avoiding the usage of complex cells in congested areas.
You can do this by setting the “congestion_avoid” attribute as true on the libcells.
The following commands set the congestion_avoid attribute on the libcells that have libpins greater than 4.
This includes both the sequential and combinational cells. You can filter combination cells if needed.
Legacy UI:
legacy_genus:/> foreach libcells_name [find / -libcell * ] { if { [llength [filter pg_type invalid [find $libcells_name -libpin * ]] ] > 4 } { set_attr congestion_avoid true $libcells_name }}
Common UI:
genus:root > get_db lib_cells -foreach { if { [llength [get_db $object .lib_pins -if { .pg_type == invalid } ]] > 4 } { set_db $object .congestion_avoid true } }
d) Creating a partial placement blockage in the congested area
When there is congestion in a specific area in the floorplan we can create a placement blockage to decrease the density of the standard cell placement in that area. Below is the command creating a partial placement blockage with density 70% at locations { 350.00 120.00 400.00 140.00 } in microns .Here the locations are provided based on the syntax {llx lly urx ury} that is { lower_left_x lower_left_y upper_right_x upper_right_y }
Legacy UI
legacy_genus:/> create_placement_blockage -name place_blck_1 -partial -boxes { 350.00 120.00 400.00 140.00 } -density 0.70
Common UI
genus:root:> create_place_blockage -name place_blck_1 -type partial -density 70 -area { 350.00 120.00 400.00 140.00 }