Pre-Placement Sanity Checks #
Before placing these standard cells, we need some checks known as pre-placement sanity checks as mentioned below. We perform these sanity checks at the pre-placement stage of the design.
- Floating pins in the netlist
- Unconstrained pins
- Undriven input ports
- Unloaded output ports
- Pin direction mismatch
- Timing
- Check physical constraints (mainly FP objects).
- PG grid check
- Check legality such as orientation, overlap etc
- Check Quality of Results (QOR).
Floating pins in the netlist
In the design, there might be a case that few pins will be floating. This means these pins are not connected to design elements. There are times when a tool optimizes a cell in which pins are floating, but the reason for floating pins can be a tool breakdown or a human error. So we need to check the floating pins before placing and optimizing. It means it hangs in the design without any connection.
Unconstrained pins
Several points in the design might not be constrained by sdc, so timing will not be checked through these pins. Hence we will miss the STA analysis for these pins. There are a few pins in the design that are intentionally false paths. This is so that STA analysis does not happen there. However, this does not mean we leave the pins unconstrained unless intended.
Undriven input port
Whether it’s a signal port, clock port, or power port, the ports must be connected. If the input port is unconnected, the input logic we get through that port will not propagate in the design. Therefore, we will miss the logic. We need to verify this port from a synthesis netlist or RTL before leaving them unconnected. The issue arises when the intended logic group for these ports does not receive any logic. Therefore, the tool may be able to optimize these logic groups as needed. Just to give you a practical example, if one key on your keyboard doesn’t work, would you like to purchase a laptop?
Unloaded output ports
The output port present in the design is not connected to any logic through the design. Therefore, there will be no output propagating through this output port. So we need to check from the synthesized netlist or RTL which is the last pin or element with which this port was connected. We will fix it, otherwise the logic about to come through a bunch of logic groups will be missed. Imagine if the key on your keyboard works but it is not resulting in your system, then you might not be purchasing this product.
Pin direction mismatch
There are basically three types of pins present in the design – input, output, and INOUT. If one of these is changed into another, like INOUT might get converted into input or output or vice versa, it will result in pin direction mismatch in the design. As a result, logic propagation is impacted and we will miss the logic as a result.
Timing
We have to check the preplacement timing before placing standard cells. If we have timing broken at this point, then we will definitely need to look into the issue and correct it to have marginal/ acceptable timing. Broken timing can be caused by a bad floorplan or constraint issues. These need to be checked and fixed.
Check physical constraints
Checking physical constraints means we need to look at the floorplan objects. We need to check whether we have all the floorplan objects and related constraints properly used. Physical constraints mean placement blockages, routing blockages, voltage area creation, physical bounds etc. If we have proper placement and routing blockages where required, then we are good. Design will converge, but if not, we might have more issues in the future. I have personally faced many issues w.r.t to this. Due to incorrect voltage area being taken in, my placement did not converge well, and my CTS was completely broken (I’ll discuss this more in CTS). Then I had to return to placement and complete this step with the corrected voltage area.
PG Grid Checks
Power/Ground has already been incorporated into the design so that all the elements present receive power in terms of energy. Many times, we miss PG distribution in some areas. We need to check and correct this otherwise the
There will be no power supply for elements in these areas. The missing PG grid tool will cause an unnecessarily long runtime during placement, resulting in legalization issues during placement.
Legality checks
Orientation, overlapping, etc., need to be checked for legality. For the objects in the design. If these issues are present, we should fix them before proceeding forward.
Quality of results
Timing groups, standard cell count, standard cell area, power information (basically leakage at this stage) will need to be further examined as QOR gives us a short summary of the design. If there is something fishy, we need to look into what we missed or check it.