Basics of Synthesis #
Synthesis is process of converting RTL (Synthesizable Verilog code) to technology specific gate level netlist (includes nets, sequential and combinational cells and their connectivity).
Once the RTL of the design fulfils all criteria of RTL checks, then the next step is synthesis. Synthesis is the stage where the RTL code is converted into a gate-level netlist. Synthesis is one of the important steps in chip designing flow as it allows us to visualize the design as it will appear after manufacturing. Here, designers review all reports and validate all required factors including timing, area, and power. Designers can make necessary changes (if required) before the creation process, which saves time, money, and effort.
Figure.1 – Synthesis Process
Synthesis Transformation Process #
1.Translate
- Process of converting RTL to equation format
- Basic Boolean optimization is carried out to reduce the literals
- Completely independent code is converted to tool dependent.
2. Map
- The obtained equations are directly mapped to the technology library
- Named technology / library binding makes design is bound to particular tool as well as technology
3. Optimize
- Technology mapped design is optimized to meet the specifications
- Various timing algorithms and architectures are involved to meet the specifications
- Design is primarily optimized to meet timing specifications
1.2 Goals of Synthesis
- To get a gate level netlist
- Inserting clock gates
- Logic optimization
- Inserting DFT logic
- Logic equivalence between RTL and netlist should be maintained
In above case LEC would pass despite of change in logic cells as even though logic cells are different at each logic cones but their output would be equivalent.