TLU File #
TLU (Timing Library Update) and TLU+ files contain timing and cell-level power information required for accurate timing analysis and power estimation in VLSI physical designs. TLU files typically include:
1. Cell Delay Tables (CDTs): These tables contain information about standard cells’ timing behavior, such as input/output delays, cell delays, and transition times.
2. Timing Arc Tables (TATs): These tables contain information about the timing behavior of non-standard cells, such as flip-flops, latches, and other complex cells.
3. Power Models: These models define the power consumption of standard cells and other library elements at different input switching rates.
TLU+ files include additional information, such as library cell models for noise and variation analysis, and constraints for advanced timing and power optimization techniques.
This file’s main functions can be summarized as follows:
1. R.C. parasitics of metal per unit length. The parasitics (R and C) are used for Net Delays. If TLU+ files are not provided, these are extracted from the .ITF file.In order to load TLU+ files, we need to load three files. These are Max TLU+, Min TLU+, and MAP files.In the MAP file, the layer and via names are mapped into the .ITF and .Tf files.
Besides the factors listed above, the tech file supports many other foundry guidelines and other useful design information.
Details:
To write out the existing tech file from icc_shell: icc_shell>write_mw_lib_files -technology -output techfile.tf
File extension is “.tf” ; # not a rigid rule 🙂
Is it possible to synthesize a design without TLUPlus files and how does the tool calculate RC information?
It is possible to synthesize a design without TLUPlus files.However, it isn’t recommended because TLUPlus files model the ultradeep submicron (UDSM) effects and have capacitance and resistance models that Are used for timing and DRC analysis; therefore, using TLUPlus files results in accurate timing. If TLUPlus files are not specified, Design Compiler calculates RC information from the technology (.tf) file.You can also use the check_tlu_plus_files command, as shown, to get information:
dc_shell-topo> check_tlu_plus_files
If you do not have TLUPlus files in the design, the check_tlu_plus_files command returns the following message:
Error: No TLU+ files were found. (PSYN-146)
If TLUPlus files are specified in the design, the check_tlu_plus_files command returns the following message:
Sanity check for TLU+ vs MW-Tech files:
Max_tlu+: max.tluplus
Min_tlu+: min.tluplus
Mapping_file: lib.map
MW design lib: TOP_LIB
——— Sanity Check on TLUPlus Files ————-
1. Checking the conducting layer names in ITF and mapping file …
[ Passed! ]
2. Checking the via layer names in ITF and mapping file …
[ Passed! ]
3. Checking the consistency of Min Width and Min Spacing between MW-tech and ITF …
[ Passed! ]
—————– Check Ends ——————
A technology file consists of several sections, each using the following syntax:
section_name {attribute_name = attribute_value…
Below are the sections of the Technological file
Section 1 :
#—————————————————-#
#Below section contains details of the technology like name, units, grid precision etc..
#—————————————————-#
Technology {
Name = “65nm” ; # technology name
Date = “2016/10/22” ; # date when this file got updated ?
dielectric = <value?> ; # value of dielectric constant of this technology ?
unitTimeName = “ps” ; # time units : though units from .lib are used for timing analysis, we still need to keep here for consistency !!
timePrecision = 1000 ; # timing precision, you can go on till 100ps , later 1ns
unitLengthName = “micron” ; # physical dimension units
lengthPrecision = 1000 ; # precision of the physical drawn length
unitVoltageName = “V” ; # voltage units : volts ==> V
unitCapacitanceName = “ff” ; # capacitance units : femto farad
capacitancePrecision = 1000000 ;
}
Section 2:
#—————————————————-#
# Declare all types of colors you may use in the design, red, green, blue etc. (RGB)
# Once you go to the metal layer definition section, you can assign these colors for metals using the “color” options.
#—————————————————-#
Color 1 {
name = “chocolate”
rgbDefined = 1
redIntensity = 100
greenIntensity = 150
blueIntensity = 200
}
Section 3:
#—————————————————-#
# TILE definitions :# Most important info: unit tiles : based on these ICC site row definitions and std cell placement happen
# Can contain more than one type of tiles to accommodate diff scenarios
#—————————————————-#
Tile “unit” {
width = 0.5 ; # min lego width : X lego value
height = 0.6 ; # min Lego height : Y logo value
}
Tile “core” {
width = 0.5 ; # same as above
height = 0.6 ; # same as above;
* we can various tile declarations as per need, while creating site rows, use the corresponding tile definition
}
Section 4:
#—————————————————-#
# Layer details:# details of layers : metal, via, diffusion , etc..: it contains : layer number , name , color, pattern, min width, pitch, etcc . drc wrto next metal/via */
#—————————————————-#
Layer “m2” { ;# layer details: layer is m0
layerNumber = xx ;# layer number that will get shown on options while doing layout edits :
;# you can say stream compatible number which gets used for lvs reporting etc.. */
maskName = “metal3” ;# mask name , can be used for verify_lvs and tech2itf comparisons. But m0 is the std names used for icc visual/internal routing
isDefaultLayer = 1 ;# to denote if this is the default layer ICC can use for physical implementation
color = “red” ;# what color do you want to see on the metal or layer
pattern = “dot” ;# what pattern : fill or dot or lines for this layer
lineStyle = “solid” ;# boundary line is solid ? or transparent etc..
visible = 1 ;# is it a visible layer
pitch = 1 ;# layer pitch, distance between center to center of m0 shapes that can be allowed
minWidth = 0.5 ;# min width of the layer that can be drawn by ICC
defaultWidth = 0.5 ;# what is the default width of the the layer
minLength = 0.5 ;# how much is the min length of m0 can be drawn
xMinSpacing = 0.5 ;# what is the min spacing in x direction that another m0 can sit
yMinSpacing = 0.5 ;# what is the min spacing in y direction that another m0 can sit
cornerMinSpacing = 0.5 ;# m2 to m2 corner in another track allowed distance at min is
minSpacing = 0.5 ;
..
nonPreferredRouteMode = 1 ;# to denote ICC whether m0 can be used for non-preferred routes if required ? 1 ==> no non-preferred routing, 0 : routing can be in any direction
orthoSpacingExcludeCorner = 1 ; # 1 means check only corner 2 corner space, not x and y as well
onWireTrack = 1 ;# details ?
yLegalWidthTblSize = 4 ;
yLegalWidthTbl = (0.5,0.6,0.7,0.8) ; # 0.046) *
}
#—————————————————-#
Layer “v2” {
layerNumber = xx
maskName = “via2”
isDefaultLayer = 1
color = “blue”
pattern = “solid”
minWidth = 0.5
minSpacing = 0
defaultWidth = 0.5
maxStackLevel = 10
onWireTrack = 1
cutTblSize = 4
cutNameTbl = (CUT1A, CUT1B,CUT1C,CUT1D)
cutWidthTbl = (0.5,0.5,0.5,0.5)
cutHeightTbl = (0.25,0.25,0.25,0.25)
enclosedCutNumNeighbor = 3
/* Enclosed cut rules */
fatTblDimension = 4
/* list down all fatTbl related rules */
}
Section 5:
#—————————————————-#
# Via Contact Codes# Via master properties like layers, resistance, enclosure etc..
#—————————————————-#
ContactCode “VIA2AB” {
contactCodeNumber = 1
cutLayer = “via2”
lowerLayer = “m1”
upperLayer = “m2”
isDefaultContact = 1
cutWidth = <value>
cutHeight = <value>
upperLayerEncWidth = 0.1
upperLayerEncHeight = 0.0
lowerLayerEncWidth = 0.1
lowerLayerEncHeight = 0.1
minCutSpacing = 0.0
unitMinResistance = 0.1
unitNomResistance = 0.1
unitMaxResistance = 0.1
}
Section 6:
#—————————————————-#
All DRs between two cuts are listed in #Via Cut Spacing Rules that operate on ICC routing engines. They include both those that are within the same layer as well as those with adjacent layers (via a set like v1-v1 and v1 > v2 etc..).
# general set of rules are : edge-edge, corner to corner and center to center of vias
#these rules can be between same net cuts (sameseg, samenet rules) or diff net cuts ( like if the cuts don’t share any immediate upper/lower metal – diffseg, diffnet rules
#As of 2012, Synopsys ICC tech file supported 16 cut rule types
#—————————————————-#
DesignRule {
layer1 = “Via1”
layer2 = “Via2”
cut1TblSize = 4
cut2TblSize = 4
cut1NameTbl = (Vsm, Vv, Vh, Vlg)
cut2NameTbl = (Vsm, Vv, Vh, Vlg)
sameNetXMinSpacingTbl = (S11,S12,S13,S14,
S21,S22,S23,S24,
S31,S32,S33,S34,
S41,S42,S43,S44)
diffNetXMinSpacingTbl = (D11,D12,D13,D14,
D21,D22,D23,D24,
D31,D32,D33,D34,
D41,D42,D43,D44)
}
All text between /* and */ is ignored.
Note : orthoSpacingExcludeCornerTbl = (1) ; # specify this if both edge-edge and corner-corner rules are present and you want the tool to consider only corner-corner rules