Electronics Revision - VLSITutor

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VLSI

6

Synthesis
Tool Command Language:
Placement
Routing
Clock Tree Synthesis
Timing:

Linux Commands

7

Linux Commands
GREP commands
AWK and CUT commands
SED commands
GVim Command
Shell Scripting
Linux commands for VLSI:

Electronics Revision

8

Diode Circuit
Transistor and Biasing
Number System
Logic Gates & logic families
FET and MOS Basics
Boolean Algebra
Sequential Logic
Combinational Logic Analysis

Introduction To VLSI

4

Semiconductor Design Overview
Digital Flow
Analog Design Flow
VLSI Fabrication

CAD for VLSI

2

TCL for VLSI
PERL for VLSI

Synthesis

9

Introduction to Synthesis
Synthesis Flow
Synthesis Inputs
Types of Synthesis
Synthesis Optimizations
QOR analysis and debug
Design For Testability
Real-time Synthesis Debug
Synthesis Tools

Physcial Design Inputs

7

Synthesized Netlist
Timing Library
Design Exchanged Format (DEF)
Unified Power Format (UPF)
Standard Design Constraint (SDC)
TLU FILE
MMMC Configuration

Floorplan

4

Introduction to Floorplan
Pin Placement
Importance of Physical Cells
Power Planning

Placement

3

Placement Overview
Pre-Placement Sanity Checks
Congestion Analysis and debug

Home
Notes
Electronics Revision

Electronics Revision

Diode Circuit
Transistor and Biasing
Number System
Logic Gates & logic families
FET and MOS Basics
Boolean Algebra
Sequential Logic
Combinational Logic Analysis

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